What do the round braces do when used outside the whole non-blocking assignment?

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What are the round braces doing in this code in Verilog?

rx_wb_valid <= (wb_memaddr <= { rx_len[(10+1):2] });

rx_wb_valid is a 1-bit register

wb_memaddr is a 10-bit register

rx_len is a 12-bit register

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Answer

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The parentheses, (), are optional in your line of code. Your code should behave the same without them. However, I think they make your code more readable since they clearly separate the left <= operator (nonblocking assignment) from the right <= operator (comparison).

The curly braces, {}, are also optional there. I think it is better to remove them in this case.

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source: stackoverflow.com
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